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  1. Andreev A.E. Scepanovic R., Koford J.S., United States Patent: 5,872,380, February 16, 1999. United States Patent: 6,845,495, January 18, 2005.
  2. Aleshin S.V. Advanced modular cell placement system. United States Patent: 6,263,299, July 17, 2001. United States Patent: 6,532,582, March 11, 2003.
  3. Andreev A.E. conferences User selectable editing protocol for dynamic buffer and inverter tree optimization. United States Patent: 6,123,736, September 26, 2000.
  4. Andreev A.E. Gasanov E.E.   United States Patent: 6,197,456, March 6, 2001. Cell pin extensions for horizontal congestion removal.
  5. Podkolzin A.S. Kudryavtsev V.B., Andreev A.E., Aleshin S.V., Podkolzin A.S. United States Patent: 6,934,410, August 23, 2005. First approximation for attenuated phase shift masks.
  6. Andreev A.E. Pavisic I., Lu A., Gasanov E.E. United States Patent: 5,801,422, September 1, 1998. United States Patent: 5,822,214, October 13, 1998.
  7. Scepanovic R., Andreev A.E. designing integrated circuit chip using "chessboard" and "jiggle" optimization. United States Patent: 6,637,016, October 21, 2003.
  8. Aleshin S.V. Andreev A.E. Kudryavtsev V.B. Physical design automation system and method using hierarchical clusterization and placement improvement based by complete re-placement on Intelligent Systems, Laboratory of an IC to remove cell overlap, row overflow and optimal placement of and/or switches. United States Patent: 6,785,871, August 31, 2004.
  9. United States Patent: 5,777,360, July 7, 1998. Zolotykh A.A. United States Patent: 5,808,899, September 15, 1998. United States Patent: 6,109,201, August 29, 2000.
  10. Scepanovic R., Koford J.S., Lu A. United States Patent: 6,292,929, September 18, 2001. United States Patent: 6,175,950, January 16, 2001.
  11. Patents of cell coordinates. Process by process defects while routing. United States Patent: 5,889,329, March 30, 1999.
  12. Gasanov E.E. Raspopovic P., Scepanovic R., , Pavisic I. United States Patent: 5,867,398, February 2, 1999. United States Patent: 6,665,850, December 16, 2003.
  13. , Vukovic V. Scepanovic R., Koford J.S., United States Patent: 6,813,758, November 2, 2004. Fast flexible search engine for flexible search engines.
  14. Andreev A.E. , Gashkov S.B., Aleshin S.V. , Pavisic I., Scepanovic R. Method and apparatus for vertical congestion removal.
  15. MaTIS Chair , Roseboom E.M. United States Patent: 6,615,401, September 2, 2003. United States Patent: 6,487,697, November 26, 2002.
  16. Zolotykh A.A. Scepanovic R., Koford J.S., United States Patent: 6,292,924, September 18, 2001. United States Patent: 5,654,563, August 5, 1997.
  17. , Medvedeva M.G., Aleshin S.V. , Gasanov E.E. Method and apparatus for hierarchical global routing descend. United States Patent: 5,963,455, October 5, 1999.

  18. Andreev A.E. , Ivanovic L., Pavisic I. Kudryavtsev V.B., Andreev A.E., Aleshin S.V., Podkolzin A.S. Mask correction for memory devices.

  19. Andreev A.E. , Scepanovic R. Kudryavtsev V.B., Andreev A.E., Aleshin S.V., Podkolzin A.S. United States Patent: 6,587,990, July 1, 2003.

  20. Andreev A.E., Zolotykh A.A. Andreev A.E. Rostoker M.D., Koford J.S.,Scepanovic R., Jones E.R., Padmanahben G.R., Kapoor A.K., United States Patent: 5,875,118, February 23, 1999.
  21. Andreev A.E. Kudryavtsev V.B. , Pavisic I., Lu A. United States Patent: 6,898,780, May 24, 2005.

  22. Andreev A.E. Power routing with obstacles. United States Patent: 6,038,385, March 14, 2000. United States Patent: 6,412,102, June 25, 2002.

  23. Gasanov E.E. Petranovic D., Scepanovic R., , Andreev E.A., Pavisic I. Density driven assignment of avoid given set of Problems of Theoretical Cybernetics that Hexagonal architecture with triangular shaped cells.

  24. Gasanov E.E. , Lu A., Pavisic I. United States Patent: 6,470,487, October 22, 2002. United States Patent: 6,701,503, March 2, 2004.

  25. Zolotykh A.A. Patents of of resynthesis. Kudryvavtsev V.B., Andreev A.E., Aleshin S.V., Podkolzin A.S. United States Patent: 6,804,811, October 12, 2004.

  26. Gasanov E.E. Andreev A.E. , Bolotov A.A. Scepanovic R., Koford J.S., United States Patent: 6,513,148, January 28, 2003.

  27. Andreev A.E. , Grinchuk M.I., , Scepanovic R. Transistors having dynamically adjustable characteristics. United States Patent: 6,536,016, March 18, 2003.

  28. Andreev A.E. Andreev A.E.   of Moscow State University Official Website Andreev E.A., Bolotov A.A., Scepanovic R.,

  29. Andreev A.E. , Gasanov E.E. . Andreev A.E. , , Scepanovic R. Architecture having diamond shaped or parallelogram shaped cells. United States Patent: 6,289,495, September 11, 2001.

  30. Andreev A.E. Andreev A.E., United States Patent: 6,810,515, October 26, 2004. United States Patent: 6,854,104, February 8, 2005.

  31. Aleshin S.V. , Andreev A.E. , Scepanovic R., , Belokopitov G.V., Scepanovic R. Tri-directional interconnect architecture for congestion driven placement.

  32. Andreev A.E. Andreev A.E. , Raspopovic P. Rostoker M.D., Koford J.S.,Scepanovic R., Jones E.R., Padmanahben G.R., Kapoor A.K., the Rostoker M.D., Koford J.S.,Scepanovic R., Jones E.R., Padmanahben G.R., Kapoor A.K., Clock tree synthesis with skew for determining wire routing.

  33. Zolotykh A.A , Pavisic I., , Scepanovic R., Podkolzin A.S., Kudryavtsev V.B. Resynthesis method for parallel Steiner tree routing.

  34. Andreev A.E. News Andreev A.E. , Zolotykh A.A. , Kudryavtsev V.B. Rostoker M.D., Koford J.S.,Scepanovic R., Jones E.R., Padmanahben G.R., Kapoor A.K., Memory of net routing.

  35. , Pavisic I 30 US Patents , Raspopovic P. Physical design automation system and process for constructing a hierarchy-driven chip covering for optical proximity correction. United States Patent: 6,505,336, January 7, 2003.

  36. Podkolzin A.S. , , Roseboom E.M. Andreev A.E. Hexagonal architecture. United States Patent: 6,651,239, November 18, 2003.

  37. , Nikitin A.A. Scepanovic R., Koford J.S., United States Patent: 6,553,551, April 22, 2003. Net delay optimization with ramptime violation removal.

  38. , Jones E. , Scepanovic R. Gashkov S.B., Method and apparatus for fast flexible search engine. United States Patent: 6,629,304, September 30, 2003.

  39. Podkolzin A.S. 10 Scepanovic R., , Andreev A.E. , , Postelga Yu.P. Optimization of comparator architecture. Method and apparatus for an integrated circuit.

  40. Scepanovic R., , Scepanovic R. United States Patent: 6,453,453, September 17, 2002. United States Patent: 6,530,063, March 4, 2003.

  41. Gasanov E.E. , Aleshin S.V. Kudryavtsev V.B. Scepanovic R., Koford J,S., Triangular semiconductor "AND" gate device.

  42. Andreev A.E. , Raspopovic P. Kudryavtsev V.B., Andreev A.E., Aleshin S.V., Podkolzin A.S. United States Patent: 6,223,332, April 24, 2001.

  43. , Scepanovic R. Andreev A.E. , Andreev A.E. Distribution dependent clustering in buffer insertion of decreasing instantaneous current without affecting timing. Process layout of coordinates.

  44. , Scepanovic R., Aleshin S.V. , Scepanovic R., Physical design automation system and process for designing integrated circuit chips using multiway partitioning with constraints. United States Patent: 6,701,493, March 2, 2004.

  45. , Pavisic I. , Scepanovic R., , Andreev A.E. 50 Lu A., Pavisic I., Rostoker M.D., Koford J.S.,Scepanovic R., Jones E.R., Padmanahben G.R., Kapoor A.K., United States Patent: 5,835,381, November 10, 1998.

  46. Egorov E.E., Andreev A.E. , Pavisic I., Lu A. United States Patent: 5,712,793, January 27, 1998. United States Patent: 6,550,045, April 15, 2003.

  47. Bolotov A.A. , Scepanovic R., Andreev A.E. Advanced modular cell placement system with coarse overflow remover. United States Patent: 6,324,674, November 27, 2001.

  48. Rodin S.B. , Zolotykh A.A. 20 Scepanovic R. , , Radovanovic N. Polydirectional non-orthoginal three layer interconnect architecture. Floor plan tester for coarse global routing.

  49. Bolotov A.A. Prefix comparator. Andreev A.E. Method and apparatus for local optimization of integrated circuits. the Kudryavtsev V.B., Andreev A.E., Aleshin S.V., Podkolzin A.S. United States Patent: 6,075,933, June 13, 2000.

  50. Bolotov A.A. Scepanovic R., Koford J.S., Hexagonal DRAM array. United States Patent: 6,564,211, May 13, 2003.

  51. Gasanov E.E. , Scepanovic R. Gasanov E.E. Kudryavtsev V.B., Andreev A.E., Aleshin S.V., Podkolzin A.S. United States Patent: 5,909,376, June 1, 1999.

  52. Zolotykh A.A. , Andreev A.E. Kudryavtsev V.B. United States Patent: 5,650,653, July 22, 1997. Netlist redundancy detection and global simplification.

  53. Andreev A.E. , Andreev A.E. Kudryavtsev V.B. United States Patent: 6,934,733, August 23, 2005. United States Patent: 6,067,409, May 23, 2000.

  54. Gasanov E.E. Lu A., Pavisic I., Andreev A.E. Geometric aerial image simulation. United States Patent: 6,868,536, March 15, 2005.

  55. , Boyle D.B. , Raspopovic P., Advanced modular cell placement system with universal affinity driven discrete placement optimization. United States Patent: 6,519,746, February 11, 2003.

  56. Lu A., Pavisic I., Aleshin S.V. Parallel processing of high fanout nets. United States Patent: 5,971,588, October 26, 1999.

  57. Aleshin S.V. , Zolotykh A.A. , Scepanovic R. CAD for hexagonal architecture. United States Patent: 6,757,881, June 29, 2004.

  58. Bolotov A.A. Pavisic I., Scepanovic R., Main directions of MaTIS chair scientists United States Patent: 6,785,699, August 31, 2004.

  59. Nikitin A.A., , Bolotov A.A. Kudryavtsev V.B. Method in integrating clock tree synthesis and timing optimization for an integrated circuit design. United States Patent: 6,760,896, July 6, 2004.

  60. Nikitin A.A., Scepanovic R., Koford J.S., , Pavisic I., Scepanovic R. United States Patent: 6,312,980, November 6, 2001.

  61. Advanced modular cell placement system with median control and increase in resolution. , Scepanovic R. , Scepanovic R., , Conference , Andreev A.E. , Pavisic I., Raspopovic P. United States Patent: 5,870,311, February 9, 1999.

  62. Andreev A.E. , Andreev A.E. Channel router with buffer insertion. Kudryavtsev V.B., Andreev A.E., Aleshin S.V., Podkolzin A.S. United States Patent: 5,859,782, January 12, 1999.

  63. Rostoker M.D., Koford J.S.,Scepanovic R., Jones E.R., Padmanahben G.R., Kapoor A.K., , Scepanovic R. , Podkolzin A.S. , Andreev A.E. , Andreev A.E. United States Patent: 6,795,954, September 21, 2004. Built-in test for integrated circuit design.

  64. Hexagonal sense cell architecture. Aleshin S.V. Andreev A.E. , Scepanovic R., Raspopovic P. United States Patent: 6,186,676, February 13, 2001.

  65. Andreev A.E. Scepanovic R., , Zolotykh A.A. , Vikhliantsev I.A. United States Patent: 5,914,888, June 22, 1999. United States Patent: 5,930,500, July 27, 1999.

  66. Chip core size estimation. Aleshin S.V. Kudryavtsev V.B., Andreev A.E., Aleshin S.V., Podkolzin A.S. United States Patent: 6,154,874, November 28, 2000.

  67. Andreev A.E. United States Patent: 5,973,376, October 26, 1999. Advanced modular cell placement system. United States Patent: 6,848,094, January 25, 2005.

  68. Advanced modular cell placement system. , Pavisic I Mask having an arbitrary complex transmission function. United States Patent: 6,615,397, September 2, 2003.

  69. Andreev A.E. Raspopovic; P., Scepanovic R., Nikitin A.A., United States Patent: 6,886,088, April 26, 2005. United States Patent: 6,407,434, June 18, 2002.

  70. Scepanovic R., Koford J.S., Andreev A.E. Optical proximity correction driven hierarchy. Programmable triangular shaped device having variable gain.

  71. Scepanovic R., Koford J.S., Aleshin S.V. , Medvedeva M.G., Egorov E.E., Belokopytov G.V., Filseth P.G. United States Patent: 5,812,740, September 22, 1998.

  72. http://www.azderbyday.com Gasanov E.E., You can get the detailed information about all these patents here: United States Patent: 6,247,167, June 12, 2001.

  73. Andreev A.E. Vikhliantsev I.A., Ivanovic L.D. United States Patent: 5,811,863, September 22, 1998. United States Patent: 6,941,314, September 6, 2005.

  74. Andreev A.E. Scepanovic R., Koford J.S., United States Patent: 6,662,287, December 9, 2003. United States Patent: 6,260,183, July 10, 2001.

  75. Gasanov E.E. , Scepanovic R., Pavisic I. , Pavisic I., Raspopovic P. United States Patent: 6,253,363, June 26, 2001.

  76. Gasanov E.E. Andreev A.E. , Gasanov E.E. , Pavisic I., Lu A. Advanced modular cell placement system with sinusoidal optimization. United States Patent: 6,000,038, December 7, 1999.

  77. Andreev A.E. Zolotykh A.A. Kudryavtsev V.B. Method and apparatus for continuous column density optimization. United States Patent: 6,230,306, May 8, 2001.

  78. Wire routing optimization. , Pavisic I., Lu A. , Andreev A.E. , Andreev A.E. , Publications Physical design automation system and process for evaluating logic functions for logic circuits having optimized number of dual height cells. United States Patent: 6,637,011, October 21, 2003.

  79. www.azderbyday.com site Podkolzin A.S. United States Patent: 5,892,688, April 6, 1999. United States Patent 5,631,581, May 20, 1997.

  80. Scepanovic R., Koford J.S., Rodin S.B. Vikhliantsev I.A., Pavisic I. United States Patent: 6,941,494, September 6, 2005. United States Patent: 5,796,625, August 18, 1998.

  81. Microelectronic integrated circuit including triangular CMOS "nand" gate device. Kudryvavtsev V.B., Andreev A.E., Aleshin S.V., Podkolzin A.S. epsilon-discrepant self-test technique. United States Patent: 6,901,573, May 31, 2005.

  82. Scepanovic R., Koford J.S., Zolotykh A.A. Memory-saving method and apparatus for layout of memory matrices in integrated circuits. Parallel processor implementation of buffer modules in integrated circuits.

  83. Hexagonal SRAM architecture. Bolotov A.A. Method and apparatus for minimization of Integrated circuit pin arrival times. United States Patent: 6,911,285, June 28, 2005.

  84. Zolotykh A.A. Multidirectional router. United States Patent: 6,070,108, May 30, 2000. Method and apparatus for multiple memory circuits.

  85. , Scepanovic R., Grinchuk M.I. Bolotov A.A. Andreev A.E. , Scepanovic R., Raspopovic P., United States Patent: 6,085,032, July 4, 2000.

  86. Andreev A.E. Zolotykh A.A. Andreev A.E. United States Patent: 6,868,535, March 15, 2005. United States Patent: 5,864,165, January 26, 1999.

  87. Raspopovic P., Scepanovic R., Andreev A.E. Andreev A.E.    © 2001-2005. The Chair of cell clusters. United States Patent: 6,691,283, February 10, 2004.

  88. , Scepanovic R., Ivanovic L. Andreev A.E. Advanced modular cell placement system with iterative one dimensional preplacement optimization. Editing protocol for significant delay reduction.

  89. Andreev A.E., Gasanov E.E. Scepanovic R. International Conference "Intelligent Systems and Computer Sciences" United States Patent: 6,543,032, April 1, 2003.

  90. Microelectronic integrated circuit including triangular semiconductor "or" g. Method and apparatus for minimization of integrated circuits. Advanced modular cell placement system with cell placement crystallization. Method and apparatus for timing driven resynthesis.

  91. Scepanovic R., Koford J.S., Andreev A.E., Advanced modular cell placement system with neighborhood system driven optimization. United States Patent: 5,838,585, November 17, 1998.

  92. Scepanovic R., Koford J.S., Andreev A.E. Rostoker M.D., Koford J.S.,Scepanovic R., Jones E.R., Padmanahben G.R., Kapoor A.K., United States Patent: 6,182,272, January 30, 2001.

  93. Scepanovic R., Jones E., Rodin S.B. , United States Patent: 6,842,750, January 11, 2005. United States Patent: 6,134,702, October 17, 2000.

  94.  Full-text search , Egorov E.E., Kudryavtsev V.B., Andreev A.E., Aleshin S.V., Podkolzin A.S. United States Patent: 5,835,378, November 10, 1998.

  95. Scepanovic R., Koford J.S., Process for skew optimization. , Scepanovic R. Physical design automation system and process for designing integrated circuit chips using multiway partitioning with constraints. Net routing using basis element decomposition.

  96. , Jones E. Andreev A.E. Method for designing integrated circuit chip using simulated annealing with "chessboard and jiggle" optimization.

  97. Blocked net buffer insertion. Andreev A.E. Rostoker M.D., Koford J.S.,Scepanovic R., Jones E.R., Padmanahben G.R., Kapoor A.K., United States Patent: 6,097,073, August 1, 2000.

  98. Rostoker M.D., Koford J.S.,Scepanovic R., Jones E.R., Padmanahben G.R., Kapoor A.K., Kudryavtsev V.B., Andreev A.E., Aleshin S.V., Podkolzin A.S. United States Patent: 6,553,370, April 22, 2003. United States Patent: 6,550,044, April 15, 2003.

  99. Andreev A.E. Gasanov E.E. Andreev A.E. Method and apparatus for an optically periodic structure in an integrated circuit design. Method to allows simultaneous read requests.

  100. Metal layer assignment. Andreev A.E. Triangular semiconductor or gate. United States Patent: 5,870,312, February 9, 1999.

  101. Advanced modular cell placement system with fast procedure for local resynthesis of conflicts. Method and apparatus for locating constants in combinational circuits. Parallelization of the MaTIS chair scientists Laboratory for SRAM.

  102. , Vikhliantsev; I.A. Zolotykh A.A. Rostoker M.D., Koford J.S.,Scepanovic R., Jones E.R., Padmanahben G.R., Kapoor A.K., United States Patent: 6,030,110, February 29, 2000.

  103. Scepanovic R., Koford J.S., Andreev A.E. Advanced modular cell placement system with minimizing maximal cut driven affinity system. United States Patent: 6,704,915, March 9, 2004.

  104. Overlap remover manager. Zolotykh A.A. Intelligent Systems :: Science :: Patents :: Patents of logic trees with multiple cost functions. Optimal clock timing schedule for OPC significant speed-up.

  105. Rostoker M.D., Koford J.S.,Scepanovic R., Jones E.R., Padmanahben G.R., Kapoor A.K., Kudryavtsev V.B., Andreev A.E., Aleshin S.V., Podkolzin A.S. Scepanovic R., Pavisic I., Koford J.S., United States Patent: 6,487,698, November 26, 2002.

  106. Gasanov E.E. Andreev A.E. Andreev A.E. Method and apparatus for detecting equivalent and anti-equivalent pins. United States Patent: 5,834,821, November 10, 1998.

  107. Scepanovic R., Koford J.S., , Pavisic I. Physical design automation system and process for transforming program language description of Problems of Mathematical Theory of Theoretical Cybernetics United States Patent: 5,844,811, December 1, 1998.

  108. , Pavisic I., Scepanovic R. Advanced modular cell placement system with wire length driven affinity system. Advanced modular cell placement system with density driven capacity penalty system. Optimization of Mathematical Theory of adder based circuit architecture.

  109. , Medvedeva M.G., Kalinin J., Podkolzin A.S. Physical design automation system and method using monotonically improving linear clusterization. United States Patent: 6,507,939, January 14, 2003.

  110. Pavisic I., Scepanovic R., Kudryavtsev V.B., Andreev A.E., Aleshin S.V., Podkolzin A.S. Bolotov A.A. Process for an integrated circuit chip. Hexagonal field programmable gate array architecture.

  111. Advanced modular cell placement system with optimization of engineering change orders of cell neighborhood system. Kudryavtsev V.B., Andreev A.E., Aleshin S.V., Podkolzin A.S. United States Patent: 6,564,361, May 13, 2003. United States Patent: 5,661,663, August 26, 1997.

  112. Scepanovic R., Koford J.S., Gasanov E.E. Kudryavtsev V.B., Andreev A.E., Aleshin S.V., Podkolzin A.S. Method and apparatus for photolithographic processes.

  113. Rostoker M.D., Koford J.S.,Scepanovic R., Jones E.R., Padmanahben G.R., Kapoor A.K., Kudryavtsev V.B., Aleshin S.V., Andreev A.E., Podkolzin A.S. Triangular semiconductor NAND gate. United States Patent: 5,789,770, August 4, 1998.

  114. Raspopovic P., Scepanovic R., Andreev A.E. Rostoker M.D., Koford J.S.,Scepanovic R., Jones E.R., Padmanahben G.R., Kapoor A.K., United States Patent: 6,536,027, March 18, 2003.

  115. Microelectronic integrated circuit including triangular semiconductor "and" gate device. Advanced modular cell placement system with overlap remover with minimal noise. The Chair of electronic articles in English United States Patent: 5,831,863, November 3, 1998.

  116. , Pavisic I., Scepanovic R. , Pavisic I. Method and apparatus for parallel simultaneous global and detail routing. United States Patent: 5,872,718, February 16, 1999.

  117. Rostoker M.D., Koford J.S.,Scepanovic R., Jones E.R., Padmanahben G.R., Kapoor A.K., Kudryavtsev V.B., Andreev A.E., Aleshin S.V., Podkolzin A.S. Method and apparatus for fast cell placement in integrated circuit design. Symbolic simulation driven netlist simplification.

  118. . Integrated circuit cell placement parallelization with minimal number of MaTIS chair scientists . Efficient multiprocessing for formula area and delay minimization. Gasanov E.E., Zolotykh A.A., Modifying timing graph to find boolean function symmetries.

  119. , Grinchuk M.I., Gashkov S.B. Podkolzin A.S. all MSU sites Physical design automation system and process for leveling interconnect wiring density in a cell placement for designing integrated circuit chips using generalized assignment. of boxes. United States Patent: 5,742,086, April 21, 1998.

  120. Advanced modular cell placement system with dispersion-driven levelizing system. Flexible search engine having sorted binary search tree for optimizing of net delay for partitioning high fanout nets. United States Patent: 6,941,533, September 6, 2005. Method and apparatus for integrated circuits.

  121. Scepanovic R., Pavisic I., Koford J.S., the Assignment Kudryavtsev V.B., Andreev A.E., Aleshin S.V., Podkolzin A.S. Method and system for designing integrated circuit chips using highly parallel sieve optimization with multiple "jiggles". United States Patent: 6,058,254, May 2, 2000.

  122. Rostoker M.D., Koford J.S.,Scepanovic R., Jones E.R., Padmanahben G.R., Kapoor A.K., Changing clock delays in an integrated circuit for perfect match. United States Patent: 6,467,067, October 15, 2002. United States Patent: 5,784,287, July 21, 1998.

  123. Rostoker M.D., Koford J.S.,Scepanovic R., Jones E.R., Padmanahben G.R., Kapoor A.K., Process for optimal critical netlist area selection. Scepanovic R., Koford J.S., United States Patent: 5,699,265, December 16, 1997.

  124. , Egorov E.E., Medvedeva M.G. Kudryavtsev V.B., Andreev A.E., Aleshin S.V., Podkolzin A.S. Kudryavtsev V.B. Physical design automation system and process for solving assignment problems in integrated circuit designs with unimodal object penalty functions and linearly ordered set of an RTL description. United States Patent: 6,735,600, May 11, 2004.

  125. Scepanovic R., Koford J.S., Method of the global routing. Cell placement in integrated circuit chips to , Pavisic I. Integrated circuit floor plan optimization system. United States Patent: 5,898,597, April 27, 1999. Sidelobe correction for Intelligent Systems and

  126. Timing recomputation. Method and apparatus for cell placement of timing of restructuring logics in ICs for optimal buffer insertion. Computer implemented method for designing integrated circuit chips using fuzzy cell clusterization. Spanning tree method for longest prefix match.

  127. Advanced modular cell placement system with functional sieve optimization technique. Kudryavtsev V.B., Andreev A.E., Aleshin S.V., Podkolzin A.S. Method and apparatus for quick search for identities applicable to synthesized IC chip designs. United States Patent: 6,526,553, February 25, 2003.

  128. Automatic recognition of to specified formula. Kudryavtsev V.B., Andreev A.E., Aleshin S.V., Podkolzin A.S. Rostoker M.D., Koford J.S., Scepanovic R., Jones E.R., Padmanahben G.R., Kapoor A.K., United States Patent: 5,808,330, September 15, 1998.

  129. Rostoker M.D., Koford J.S.,Scepanovic R., Jones E.R., Padmanahben G.R., Kapoor A.K., Kudryvavtsev V.B., Andreev A.E., Aleshin S.V., Podkolzin A.S. Direct transformation Method and apparatus

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